rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a cmos dual 8-bit buffered multiplying dac ad7528 features on-chip latches for both dacs +5 v to +15 v operation dacs matched to 1% four quadrant multiplication ttl/cmos compatible latch free (protection schottkys not required) applications digital control of: gain/attenuation filter parameters stereo audio circuits x-y graphics functional block diagram v ref a ad7528 v ref b r fb b agnd v dd db0 db7 data inputs dac a / dac b cs wr dgnd control logic input buffer latch latch out b out a dac b dac a r fb a general description the ad7528 is a monolithic dual 8-bit digital/analog converter featuring excellent dac-to-dac matching. it is available in skinny 0.3" wide 20-lead dips and in 20-lead surface mount packages. separate on-chip latches are provided for each dac to allow easy microprocessor interface. data is transferred into either of the two dac data latches via a common 8-bit ttl/cmos compatible input port. control input dac a /dac b determines which dac is to be loaded. the ad7528s load cycle is similar to the write cycle of a ran- dom access memory and the device is bus compatible with most 8-bit microprocessors, including 6800, 8080, 8085, z80. the device operates from a +5 v to +15 v power supply, dis- sipating only 20 mw of power. both dacs offer excellent four quadrant multiplication charac- teristics with a separate reference input and feedback resistor for each dac. product highlights 1. dac-to-dac matching: since both of the ad7528 dacs are fabricated at the same time on the same chip, precise match- ing and tracking between dac a and dac b is inherent. the ad7528s matched cmos dacs make a whole new range of applications circuits possible, particularly in the audio, graphics and process control areas. 2. small package size: combining the inputs to the on-chip dac latches into a common data bus and adding a dac a /dac b select line has allowed the ad7528 to be packaged in either a small 20-lead dip, soic or plcc. ordering guide 1 temperature relative gain package model 2 ranges accuracy error options 3 ad7528jn C40 c to +85 c 1 lsb 4 lsb n-20 ad7528kn C40 c to +85 c 1/2 lsb 2 lsb n-20 ad7528ln C40 c to +85 c 1/2 lsb 1 lsb n-20 ad7528jp C40 c to +85 c 1 lsb 4 lsb p-20a ad7528kp C40 c to +85 c 1/2 lsb 2 lsb p-20a ad7528lp C40 c to +85 c 1/2 lsb 1 lsb p-20a ad7528jr C40 c to +85 c 1 lsb 4 lsb r-20 ad7528kr C40 c to +85 c 1/2 lsb 2 lsb r-20 ad7528lr C40 c to +85 c 1/2 lsb 1 lsb r-20 ad7528aq C40 c to +85 c 1 lsb 4 lsb q-20 ad7528bq C40 c to +85 c 1/2 lsb 2 lsb q-20 ad7528cq C40 c to +85 c 1/2 lsb 1 lsb q-20 ad7528sq C55 c to +125 c 1 lsb 4 lsb q-20 ad7528tq C55 c to +125 c 1/2 lsb 2 lsb q-20 ad7528uq C55 c to +125 c 1/2 lsb 1 lsb q-20 notes 1 analog devices reserves the right to ship side-brazed ceramic in lieu of cerdip. parts will be marked with cerdip designator q. 2 processing to mil-std-883c, class b is available. to order, add suffix /883b to part number. for further information, see analog devices 1990 military products databook. 3 n = plastic dip; p = plastic leaded chip carrier; q = cerdip; r = soic. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998
rev. b C2C ad7528Cspecifications (v ref a = v ref b = +10 v; out a = out b = o v unless otherwise noted) v dd = +5 v v dd = +15 v parameter version 1 t a = +25 ct min , t max t a = +25 ct min , t max units test conditions/comments static performance 2 resolution all 8 8 8 8 bits relative accuracy j, a, s 1 1 1 1 lsb max this is an endpoint linearity specification k, b, t 1/2 1/2 1/2 1/2 lsb max l, c, u 1/2 1/2 1/2 1/2 lsb max differential nonlinearity all 1 1 1 1 lsb max all grades guaranteed monotonic over full operating temperature range gain error j, a, s 4 6 4 5 lsb max measured using internal r fb a and r fb b k, b, t 2 4 2 3 lsb max both dac latches loaded with 11111111 l, c, u 1 3 1 1 lsb max gain error is adjustable using circuits of figures 4 and 5 gain temperature coefficient 3 d gain/ d temperature all 0.007 0.007 0.0035 0.0035 %/ c max output leakage current out a (pin 2) all 50 400 50 200 na max dac latches loaded with 00000000 out b (pin 20) all 50 400 50 200 na max input resistance (v ref a, v ref b) all 8 8 8 8 k w min input resistance tc = C300 ppm/ c, typical 15 15 15 15 k w max input resistance is 11 k w v ref a/v ref b input resistance match all 1 1 1 1% max digital inputs 4 input high voltage v ih all 2.4 2.4 13.5 13.5 v min input low voltage v il all 0.8 0.8 1.5 1.5 v max input current i in all 1 10 1 10 m a max v in = 0 or v dd input capacitance db0Cdb7 all 10 10 10 10 pf max wr , cs , dac a /dac b all 15 15 15 15 pf max switching characteristics 3 see timing diagram chip select to write set up time t cs all 90 100 60 80 ns min chip select to write hold time t ch all 0 0 10 15 ns min dac select to write set up time t as all 90 100 60 80 ns min dac select to write hold time t ah all 0 0 10 15 ns min data valid to write set up time t ds all 80 90 30 40 ns min data valid to write hold time t dh all 0 0 0 0 ns min write pulsewidth t wr all 90 100 60 80 ns min power supply see figure 3 i dd all 2 2 2 2 ma max all digital inputs v il or v ih all 100 500 100 500 m a max all digital inputs 0 v or v dd ac performance characteristics 5 v dd = +5 v v dd = +15 v parameter version 1 t a = +25 ct min , t max t a = +25 ct min , t max units test conditions/comments dc supply rejection ( d gain/ d v dd ) all 0.02 0.04 0.01 0.02 % per % max d v dd = 5% current settling time 2 all 350 400 180 200 ns max to 1/2 lsb. out a/out b load = 100 w . wr = cs = 0 v. db0Cdb7 = 0 v to v dd or v dd to 0 v propagation delay (from digital in- v ref a = v ref b = +10 v put to 90% of final analog output current) all 220 270 80 100 ns max out a, out b load = 100 w c ext = 13 pf wr = cs = 0 v db0Cdb7 = 0 v to v dd or v dd to 0 v digital-to-analog glitch impulse all 160 440 nv sec typ for code transition 00000000 to 11111111 output capacitance c out a all 50 50 50 50 pf max dac latches loaded with 00000000 c out b 50 505050pf max c out a 120 120 120 120 pf max dac latches loaded with 11111111 c out b 120 120 120 120 pf max ac feedthrough 6 v ref a to out a all C70 C65 C70 C65 db max v ref a, v ref b = 20 v p-p sine wave v ref b to out b C70 C65 C70 C65 db max @ 100 khz (measured using recommended p.c. board layout (figure 7) and ad644 as output amplifiers)
plcc 3 2 1 20 19 9 10 11 12 13 18 17 16 15 14 4 5 6 7 8 top view (not to scale) pin 1 identifier v ref a dgnd dac a /dac b (msb) db7 db6 v ref b v dd wr cs db0 (lsb) ad7528 r fb a out a agnd out b r fb b db5 db4 db3 db2 db1 v dd = +5 v v dd = +15 v parameter version 1 t a = +25 ct min , t max t a = +25 ct min , t max units test conditions/comments channel-to-channel isolation both dac latches loaded with 11111111. v ref a to out b all C77 C77 db typ v ref a = 20 v p-p sine wave @ 100 khz v ref b = 0 v see figure 6. v ref b to out a C77 C77 db typ v ref a = 20 v p-p sine wave @ 100 khz v ref a = 0 v see figure 6. digital crosstalk all 30 60 nv sec typ measured for code transition 00000000 to 11111111 harmonic distortlon all C85 C85 db typ v in = 6 v rms @ 1 khz notes 1 temperature ranges are j, k, l versions: C40 c to +85 c a, b, c versions: C40 c to +85 c s, t, u versions: C55 c to +125 c 2 specifications applies to both dacs in ad7528. 3 guaranteed by design but not production tested. 4 logic inputs are mos gates. typical input current (+25 c) is less than 1 na. 5 these characteristics are for design guidance only and are not subject to test. 6 feedthrough can be further reduced by connecting the metal lid on the ceramic package (suffix d) to dgnd. specifications subject to change without notice. ad7528, ideal maximum output is v ref C 1 lsb. gain error of both dacs is adjustable to zero with external resistance. output capacitance capacitance from out a or out b to agnd. digital to analog glitch lmpulse the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is normally specified as the area of the glitch in either pa-secs or nv-secs depending upon whether the glitch is measured as a current or voltage signal. glitch impulse is measured with v ref a, v ref b = agnd. propagation delay this is a measure of the internal delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 90% of its final value. channel-to-channel isolation the proportion of input signal from one dacs reference input which appears at the output of the other dac, expressed as a ratio in db. digital crosstalk the glitch energy transferred to the output of one converter due to a change in digital input code to the other converter. speci- fied in nv secs. pin configurations absolute maximum ratings (t a = +25 c unless otherwise noted) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, +17 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, +17 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . v dd + 0.3 v dgnd to agnd . . . . . . . . . . . . . . . . . . . . . . . . v dd + 0.3 v digital input voltage to dgnd . . . . . . . C0.3 v, v dd + 0.3 v v pin2 , v pin20 to agnd . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v v ref a, v ref b to agnd . . . . . . . . . . . . . . . . . . . . . . . 25 v v rfb a, v rfb b to agnd . . . . . . . . . . . . . . . . . . . . . . . 25 v power dissipation (any package) to +75 c . . . . . . . 450 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . 6 mw/ c operating temperature range commercial (j, k, l) grades . . . . . . . . . . . C40 c to +85 c industrial (a, b, c) grades . . . . . . . . . . . . C40 c to +85 c extended (s, t, u) grades . . . . . . . . . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . +300 c caution: 1. esd sensitive device. the digital control inputs are diode protected; however, permanent damage may occur on uncon- nected devices subjected to high energy electrostatic fields. unused devices must be stored in conductive foam or shunts. 2. do not insert this device into powered sockets. remove power before insertion or removal. terminology relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero and full scale and is normally expressed in lsbs or as a percentage of full scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb max over the operating temperature range ensures monotonicity. gain error gain error or full-scale error is a measure of the output error between an ideal dac and the actual device output. for the ad7528 rev. b C3C dip, soic top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad7528 db4 db5 db6 out a r fb a v ref a (msb) db7 dac a /dac b dgnd db3 db2 db1 r fb b v ref b v dd db0 (lsb) cs wr agnd out b
ad7528 rev. b C4C interface logic information dac selection: both dac latches share a common 8-bit input port. the con- trol input dac a /dac b selects which dac can accept data from the input port. mode selection: inputs cs and wr control the operating mode of the selected dac. see mode selection table below. write mode: when cs and wr are both low the selected dac is in the write mode. the input data latches of the selected dac are transpar- ent and its analog output responds to activity on db0Cdb7. hold mode: the selected dac latch retains the data which was present on db0Cdb7 just prior to cs or wr assuming a high state. both analog outputs remain at the values corresponding to the data in their respective latches. mode selection table dac a /dac b cs wr dac a dac b l l l write hold h l l hold write x h x hold hold x x h hold hold l = low state; h = high state; x = dont care. write cycle timing diagram v dd t dh v ih v il t ds t wr t as t ah t cs t ch v dd v dd v dd 0 0 0 0 chip select dac a /dac b write data in (db0 C db7) data in stable notes: 1. all input signal rise and fall times measured from 10% to 90% of v dd . v dd = +5v, t r = t f = 20ns; v dd = +15v, t r = t f = 40ns; 2. timing measurement reference level is v ih + v il 2 circuit informationd/a section the ad7528 contains two identical 8-bit multiplying d/a con- verters, dac a and dac b. each dac consists of a highly stable thin film r-2r ladder and eight n-channel current steer- ing switches. a simplified d/a circuit for dac a is shown in v ref a agnd dac a data latches and drivers 2r s1 2r s2 2r s3 2r s8 2r r r r out a r fb a r figure 1. simplified functional circuit for dac a figure 1. an inverted r-2r ladder structure is used, that is, bi- nary weighted currents are switched between the dac output and agnd thus maintaining fixed currents in each ladder leg independent of switch state. equivalent circuit analysis figure 2 shows an approximate equivalent circuit for one of the ad7528s d/a converters, in this case dac a. a similar equivalent circuit can be drawn for dac b. note that agnd (pin 1) is common for both dac a and dac b. the current source i leakage is composed of surface and junc- tion leakages and, as with most semiconductor devices, approxi- mately doubles every 10 c. the resistor r o as shown in figure 2 is the equivalent output resistance of the device which varies with input code (excluding all 0s code) from 0.8 r to 2 r. r is typically 11 k w . c out is the capacitance due to the n-channel switches and varies from about 50 pf to 120 pf depending upon the digital input. g(v ref a, n) is the thevenin equivalent voltage generator due to the reference input voltage v ref a and the transfer function of the r-2r ladder. r fb a agnd out a r o g(v ref a, n) i lkg c out r figure 2. equivalent analog output circuit of dac a circuit informationCdigital section the input buffers are simple cmos inverters designed such that when the ad7528 is operated with v dd = 5 v, the buffer converts ttl input levels (2.4 v and 0.8 v) into cmos logic levels. when v in is in the region of 2.0 volts to 3.5 volts the input buffers operate in their linear region and pass a quiescent current, see figure 3. to minimize power supply currents it is recommended that the digital input voltages be as close to the supply rails (v dd and dgnd) as is practically possible. the ad7528 may be operated with any supply voltage in the range 5 v dd 15 volts. with v dd = +15 v the input logic levels are cmos compatible only, i.e., 1.5 v and 13.5 v. v in C volts 800 0 i dd m a (v dd = +5v) 1 2 3 4 5 6 7 8 9 10 11 13 14 12 700 600 500 400 300 200 100 i dd ma (v dd = +15v) 9 8 7 6 5 4 3 2 1 v dd = +5v v dd = +15v t a = +25 8 c all digital inputs tied together figure 3. typical plots of supply current, i dd vs. logic input voltage v in , for v dd = +5 v and +15 v
ad7528 rev. b C5C table i. unipolar binary code table dac latch contents analog output msb lsb (dac a or dac b) 1 1 1 1 1 1 1 1 v in 255 256 ? ? ? ? 1 0 0 0 0 0 0 1 v in 129 256 ? ? ? ? 1 0 0 0 0 0 0 0 v in 128 256 ? ? ? ? =- v in 2 0 1 1 1 1 1 1 1 v in 127 256 ? ? ? ? 0 0 0 0 0 0 0 1 v in 1 256 ? ? ? ? 0 0 0 0 0 0 0 0 v in 0 256 ? ? ? ? = 0 note: 1 lsb = 2 - 8 () v in () = 1 256 v in () table ii. bipolar (offset binary) code table dac latch contents analog output msb lsb (dac a or dac b) 1 1 1 1 1 1 1 1 + v in 127 128 ? ? ? ? 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 v in 1 128 ? ? ? ? 0 0 0 0 0 0 0 1 v in 127 128 ? ? ? ? 0 0 0 0 0 0 0 0 v in 128 128 ? ? ? ? note: 1 lsb = 2 - 7 () v in () = 1 128 v in () table iii. recommended trim resistor values vs. grade trim resistor j/a/s k/b/t l/c/u r1; r3 1 k 500 200 r2; r4 330 150 82 v in a ( 10v) ad7528 v in b ( 10v) r fb b agnd v dd db0 db7 data inputs dac a / dac b cs wr dgnd control logic input buffer out b latch r4 1 dac b c2 2 r3 1 dac a latch v out b agnd r fb a out a r2 1 c1 2 v out a agnd r1 1 notes: 1 r1, r2 and r3, r4 used only if gain adjustment is required. see table iii for recommended values. 2 c1, c2 phase compensation (10pfC15pf) is required when using high speed amplifiers to prevent ringing or oscillation. figure 4. dual dac unipolar binary operation (2 quadrant multiplication); see table i v in a ( 10v) ad7528 v in b ( 10v) r fb b agnd v dd db0 db7 data inputs dac a / dac b cs wr dgnd control logic input buffer out b latch r4 1 dac b c2 3 r3 1 dac a latch v out b agnd r fb a out a r2 1 c1 3 v out a agnd r1 1 a1 r7 2 10k v r6 2 20k v a2 r5 20k v r11 5k v agnd r10 2 20k v r9 2 10k v a4 r8 20k v r12 5k v agnd a3 notes: 1 r1, r2 and r3, r4 used only if gain adjustment is required. see table iii for recommended values. adjust r1 for v out a = 0v with code 10000000 in dac a latch. adjust r3 for v out b = 0v with code 10000000 in dac b latch. 2 matching and tracking is essential for resistor pairs r6, r7 and r9, r10. 3 c1, c2 phase compensation (10pfC15pf) may be required if a1/a3 is a high speed amplifier. figure 5. dual dac bipolar operation (4 quadrant multiplication); see table ii
ad7528 rev. b C6C applications information application hints to ensure system performance consistent with ad7528 specifi- cations, careful attention must be given to the following points: 1. general ground management: ac or transient voltages between the ad7528 agnd and dgnd can cause noise injection into the analog output. the simplest method of ensuring that voltages at agnd and dgnd are equal is to tie agnd and dgnd together at the ad7528. in more complex systems where the agndCdgnd intertie is on the backplane, it is recommended that diodes be connected in inverse parallel between the ad7528 agnd and dgnd pins (1n914 or equivalent). 2. output amplifier offset: cmos dacs exhibit a code-dependent output resistance which in turn causes a code-dependent amplifier noise gain. the effect is a code- dependent differential nonlinearity term at the amplifier output which depends on v os (v os is amplifier input offset voltage). this differential nonlinearity term adds to the r/2r differential nonlinearity. to maintain monotonic operation, it is recommended that amplifier v os be no greater than 10% of 1 lsb over the temperature range of interest. 3. high frequency considerations: the output capacitance of a cmos dac works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. this can cause ringing or oscillation. stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor. dynamic performance the dynamic performance of the two dacs in the ad7528 will depend upon the gain and phase characteristics of the output amplifiers together with the optimum choice of the pc board layout and decoupling components. figure 6 shows the relation input frequency C hz C100 isolation C db 20k 50k 100k 200k 1m 500k C90 C80 C70 C60 C50 t a = +25 8 c v dd = +15v v in = 20v peak to peak figure 6. channel-to-channel isolation agnd v+ vC ad644 v ref b* v dd cs lsb c1 location c2 location v ref a* dgnd dac a /dac b msb pin 8 of to-5 can (ad644) ad7528 pin 1 wr ad7528 *note input screens to reduce feedthrough. layout shows copper side (i.e., bottom view). figure 7. suggested pc board layout for ad7528 with ad644 dual op amp ship between input frequency and channel to channel isolation. figure 7 shows a printed circuit layout for the ad7528 and the ad644 dual op amp which minimizes feedthrough and crosstalk. single supply applications the ad7528 dac r-2r ladder termination resistors are con- nected to agnd within the device. this arrangement is par- ticularly convenient for single supply operation because agnd may be biased at any voltage between dgnd and v dd . figure 8 shows a circuit which provides two +5 v to +8 v analog out- puts by biasing agnd +5 v up from dgnd. the two dac reference inputs are tied together and a reference input voltage is obtained without a buffer amplifier by making use of the constant and matched impedances of the dac a and dac b reference inputs. current flows through the two dac r-2r ladders into r1 and r1 is adjusted until the v ref a and v ref b inputs are at +2 v. the two analog output voltages range from +5 v to +8 v for dac codes 00000000 to 11111111. v out a = +5v to +8v v dd data inputs dac a /dac b cs wr gnd v dd = +15v suggested op amp: ad644 v out b = +5v to +8v r1 10k v 2 volts r2 1k v ad584j ad7528 db0 db7 dac a dac b figure 8. ad7528 single supply operation figure 9 shows dac a of the ad7528 connected in a positive reference, voltage switching mode. this configuration is useful in that v out is the same polarity as v in allowing single supply operation. however, to retain specified linearity, v in must be in the range 0 v to +2.5 v and the output buffered or loaded with a high impedance, see figure 10. note that the input voltage is connected to the dac out a and the output voltage is taken from the dac v ref a pin. v ref a v in (0v to +2.5v) v dd +15v ad7528 dac a out a v out figure 9. ad7528 in single supply, voltage switching mode v in a C volts 3 2.5 error C lsb 3.5 34567 2 1 t a = +25 8 c v dd = +15v 4.5 5.5 6.5 7.5 nonlinearity differential nonlinearity figure 10. typical ad7528 performance in single supply voltage switching mode (k/b/t, l/c/u grades)
ad7528 rev. b C7C circuit equations ccrrr r 121245 == = ,, f rc q r r r r a r r c f fbb o f s = = = 1 211 3 4 1 p note dac equivalent resistance equals 256 () dac ladder sis ce dac digital code r e tan microprocessor interface address bus a** a + 1** address decode logic dac a /dac b cs dac a db0 db7 wr v ma f 2 ad7528* dac b data bus d0Cd7 a0Ca15 cpu 6800 *analog circuitry has been omitted for clarity **a = decoded 7528 addr dac a a + 1 = decoded 7528 addr dac b figure 11. ad7528 dual dac to 6800 cpu interface address bus a** a + 1** dac a /dac b cs dac a db0 db7 wr ad7528* dac b addr/data bus ad0Cad7 a8Ca15 cpu 8085 *analog circuitry has been omitted for clarity **a = decoded 7528 addr dac a a + 1 = decoded 7528 addr dac b note: 8085 instruction shld (store h & l direct) can update both dacs with data from h and l registers address decode logic latch 8212 wr ale figure 12. ad7528 dual dac to 8085 cpu interface programmable window comparator v ref a r fb a v cc data inputs dac a /dac b cs wr pass/ fail output 1k v ad7528 db0 db7 dac a dac b out a v dd v ref b +v ref r fb b 3 2 7 ad311 comparator out b 3 2 7 ad311 comparator test input 0 to Cv ref figure 13. digitally programmable window comparator (upper and lower limit detector) programmable state variable filter in this state variable or universal filter configuration (figure 14) dacs a1 and b1 control the gain and q of the filter character- istic while dacs a2 and b2 control the cutoff frequency, f c . dacs a2 and b2 must track accurately for the simple expres- sion for f c to hold. this is readily accomplished by the ad7528. op amps are 2 ad644. c3 compensates for the effects of op amp gain bandwidth limitations. dac a /dac b cs wr v in v dd db0Cdb7 data 1 dac b1 r f ad7528 dac a /dac b cs wr a3 v dd db0Cdb7 data 2 ad7528 a2 a1 r3 10k v dac a1 r s dac a2 r1 high pass output r4 30k v r5 30k v c3 47pf c1 1000pf dac b2 r2 a4 c2 1000pf low pass output band pass output figure 14. digitally controlled state variable filter the filter provides low pass, high pass and band pass outputs and is ideally suited for applications where microprocessor control of filter parameters is required, e.g., equalizer, tone controls, etc. programmable range for component values shown is f c = 0 khz to 15 khz and q = 0.3 to 4.5. in the circuit of figure 13 the ad7528 is used to implement a programmable window comparator. dacs a and b are loaded with the required upper and lower voltage limits for the test, respectively. if the test input is not within the programmed limits, the pass/fail output will indicate a fail (logic zero).
ad7528 rev. b C8C c681eC0C9/98 printed in u.s.a. digitally controlled dual telephone attenuator in this configuration the ad7528 functions as a 2-channel digi- tally controlled attenuator. ideal for stereo audio and telephone signal level control applications. table iv gives input codes vs. attenuation for a 0 db to 15.5 db range. input code = 256 3 10 exp - ? ? ? ? attenuation db , 20 v in b v out a v in a data bus dac a /dac b cs wr ad7528 db0 db7 dac a dac b v dd v out b a1 a2 suggested op amp: ad644 figure 15. digitally controlled dual telephone attenuator table iv. attenuation vs. dac a, dac b code for the circuit of figure 15 attn. dac input code in attn. dac input code in db code decimal db code decimal 0.0 1 1 1 1 1 1 1 1 255 8 8.0 0 1 1 0 0 1 1 0 102 0.5 1 1 1 1 0 0 1 0 242 8 8.5 0 1 1 0 0 0 0 0 96 1.0 1 1 1 0 0 1 0 0 228 8 9.0 0 1 0 1 1 0 1 1 91 1.5 1 1 0 1 0 1 1 1 215 8 9.5 0 1 0 1 0 1 1 0 86 2.0 1 1 0 0 1 0 1 1 203 10.0 0 1 0 1 0 0 0 1 81 2.5 1 1 0 0 0 0 0 0 192 10.5 0 1 0 0 1 1 0 0 76 3.0 1 0 1 1 0 1 0 1 181 11.0 0 1 0 0 1 0 0 0 72 3.5 1 0 1 0 1 0 1 1 171 11.5 0 1 0 0 0 1 0 0 68 4.0 1 0 1 0 0 0 1 0 162 12.0 0 1 0 0 0 0 0 0 64 4.5 1 0 0 1 1 0 0 0 152 12.5 0 0 1 1 1 1 0 1 61 5.0 1 0 0 1 0 0 0 0 144 13.0 0 0 1 1 1 0 0 1 57 5.5 1 0 0 0 1 0 0 0 136 13.5 0 0 1 1 0 1 1 0 54 6.0 1 0 0 0 0 0 0 0 128 14.0 0 0 1 1 0 0 1 1 51 6.5 0 1 1 1 1 0 0 1 121 14.5 0 0 1 1 0 0 0 0 48 7.0 0 1 1 1 0 0 1 0 114 15.0 0 0 1 0 1 1 1 0 46 7.5 0 1 1 0 1 1 0 0 108 15.5 0 0 1 0 1 0 1 1 43 for further applications information the reader is referred to analog devices application note on the ad7528. 20-lead cerdip (q-20) 0.97 (24.64) 0.935 (23.75) seating plane 0.02 (0.5) 0.016 (0.41) 0.07 (1.78) 0.05 (1.27) 0.15 (3.8) 0.125 (3.18) 0.20 (5.0) 0.14 (3.56) 0.11 (2.79) 0.09 (2.28) 20 110 11 0.28 (7.11) 0.24 (6.1) pin 1 0.14 (3.56) 0.125 (3.17) 15 8 0 8 0.32 (8.128) 0.29 (7.366) 0.011 (0.28) 0.009 (0.23) lead no. 1 identified by dot or notch leads are solder or tin-plated kovar or alloy 42 outline dimensions dimensions shown in inches and (mm). 20-lead plastic dip (n-20) seating plane 0.021 (0.533) 0.015 (0.381) 0.065 (1.66) 0.045 (1.15) 0.11 (2.79) 0.09 (2.28) 0.145 (3.683) min 0.125 (3.175) min 20 110 11 pin 1 1.07 (27.18) max 0.255 (6.477) 0.245 (6.223) 0.32 (8.128) 0.30 (7.62) 0.011 (0.28) 0.009 (0.23) 0.135 (3.429) 0.125 (3.17) 15 8 0 8 lead no. 1 identified by dot or notch leads are solder or tin-plated kovar or alloy 42 20-lead soic (r-20) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc
package/price information cmos dual 8-bit buffered multiplying dac model status package description pin count temperature range price* (100-499) 5962-8770101ra production cerdip glass seal 20 military $32.98 5962-87701022a production cer. leadless chip carrier 20 military $53.29 5962-8770102ra production cerdip glass seal 20 military $35.21 5962-87701032a production cer. leadless chip carrier 20 military $61.32 5962-8770103ra production cerdip glass seal 20 military $39.26 ad7528achips production chips/die sales 20 industrial $8.05 ad7528aq production cerdip glass seal 20 industrial - ad7528bchips production chips/die sales 20 industrial $8.32 ad7528bq production cerdip glass seal 20 industrial - ad7528cq production cerdip glass seal 20 industrial - ad7528jn production plastic/epoxy dip 20 commercial $6.19 ad7528jn/+ obsolete plastic/epoxy dip 20 commercial - ad7528jp production plastic lead chip carrier 20 commercial $7.07 ad7528jp-reel production plastic lead chip carrier 20 commercial - ad7528jr production std s.o. pkg (soic) 20 commercial $7.07 ad7528jr-reel production std s.o. pkg (soic) 20 commercial - ad7528jr-reel7 production std s.o. pkg (soic) 20 commercial - ad7528kn production plastic/epoxy dip 20 commercial $6.40 ad7528kp production plastic lead chip carrier 20 commercial $7.35 ad7528kp-reel production plastic lead chip carrier 20 commercial - ad7528ln production plastic/epoxy dip 20 commercial $10.35 ad7528lp production plastic lead chip carrier 20 commercial $11.80 ad7528lr production std s.o. pkg (soic) 20 commercial $11.80
* this price is provided for budgetary purposes as recommended list price in u.s. dollars per unit in the stated volume. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view pricing and availability for further information. ad7528lr-reel production std s.o. pkg (soic) 20 commercial - ad7528lrs obsolete shrink so package 20 commercial - ad7528lrs-reel obsolete shrink so package 20 commercial - AD7528SCHIPS production chips/die sales 20 military $15.70 ad7528sq production cerdip glass seal 20 military - ad7528tq production cerdip glass seal 20 military -
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